Presently, most dynamic random access memory (DRAM) manufacturers form a capacitor above a silicon substrate so as to form the storage capacitor. The number of capacitors that can be fit on a single chip determines the number of bits that can be stored within the device. As the need for more memory increases, the need arises to shrink all of the devices which makes up the memory circuitry. Hence, it is desirable to reduce the physical size of the capacitor.
Despite the need to shrink the physical size of each memory cell, the actual capacitance of each memory cell must not significantly decrease. A significant decrease in the capacitance of the memory cell will cause the soft error rate to increase. The soft error rate is a measure of the rate of errors (misread or miswritten data) which are not the direct result of damage to the DRAM. One cause for the increase in soft error rate relates to the large difference in capacitance between the bitlines and the storage cells. Typically, the bitlines have a much higher capacitance than each memory cell. Therefore, using simple voltage division, small changes in the capacitance of the bitlines will cause errors when data is read from or stored to a storage cell, especially when the voltage level stored in the cell has degraded due to losses in the storage cell. Hence, it is preferable to increase the capacitance of each memory cell so that the soft error rate is decreased.
Many DRAM manufacturers have manipulated the structure and composition of the memory cells so as to increase the capacitance of the memory cells as well as to shrink their physical size. In an effort to increase the capacitance of the storage cell, some manufacturers have tried "stacked capacitors" or "crown cell" cell capacitors. Each of these attempt to increase the capacitance per unit area by extending the capacitor in the vertical direction instead of the lateral direction. An example of a "crown cell" is given in provisionally filed patent applications Ser. No. 60/036,998 (TI-21973) and Ser. No. 60/037,247 (TI-21537), both are incorporated herein by reference.
Another approach to increase the capacitance of the storage cell while using less lateral area involves the use of "rugged polysilicon" to form the bottom electrode of the storage cell. More specifically, the bottom electrode is formed of a polysilicon layer which has features that extend between 70 and 100 nm. For examples of this type of rugged polysilicon ("rugged poly") see U.S. Pat. Nos. 5,385,863, 5,561,311, 5,554,557 and 5,445,999.